1. Technical Field
The inventive concept relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device including a bit line and a storage node contact plug.
2. Related Art
Dynamic random access memories (DRAMs) of semiconductor storage devices include a plurality of unit cells, each of which includes a capacitor and a transistor. The capacitor is used to temporarily store data, and the transistor is used to transfer data between a bit line and the capacitor in response to a control signal delivered through a word line. The transistor comprises three regions of a gate, a source, and a drain. Charges move between the source and the drain according to the control signal input to the gate. The charges move between the source and the drain through a channel region.
When a conventional transistor is fabricated on a semiconductor substrate, a gate is formed in a semiconductor substrate, and a source and a drain are formed by doping the semiconductor substrate with impurities on either side of the gate. A region of the semiconductor substrate below the gate between the source and the drain becomes a channel region of the transistor. A transistor with a horizontal channel region occupies a constant area of the semiconductor substrate. In a complex semiconductor storage device, it is difficult to reduce the total area due to the amount of space occupied by transistors.
When the total area of a semiconductor storage device is reduced, the number of the semiconductor storage devices that can be made from a single wafer is increased, resulting in an overall improvement in production yields.
Various methods for reducing the total area of a semiconductor storage device have been suggested. One of these methods is a recess gate, in which a recess is formed in a semiconductor substrate, and a channel region is formed along a portion of the recess.
A buried gate in which a gate is formed to be entirely buried within a recess has been studied. In a buried gate structure, a bit line is disposed between two storage node contact plugs. As dimensions of the device are reduced, the distance between a bit line and the storage node contact plug decreases, resulting in increased capacitance and reduced sensing margins. As the sensing margin is reduced, cell characteristics including the record recovery time (tWR) are degraded.